TY - JOUR
T1 - Four-level quasi-nested inverter topology for single-phase applications
AU - Reusser, Carlos A.
AU - Young, Hector
N1 - Funding Information:
Funding: This research received financial support from the Chilean Found for Human Resource Development (ANID) through its Ph.D. scholarships (CONICYT/21130448) and from the Research Direction of the Universidad de La Frontera.
Funding Information:
Acknowledgments: The authors wish to thank the support of the Electrical Engineering School, Pontificia Universidad Catolica de Valparaiso, and also the support provided by the Advanced Center for Electrical and Electronic Engineering AC3E (ANID/FB0008) of Universidad Tecnica Federico Santa Maria.
Publisher Copyright:
© 2021 by the authors. Licensee MDPI, Basel, Switzerland.
PY - 2021/2/1
Y1 - 2021/2/1
N2 - In this paper, a novel four-level single-phase multilevel converter is introduced, consisting of six active switches arranged in a quasi-nested configuration. The proposed topology synthesizes its output voltage levels with respect to a floating neutral point, using four cascaded capacitors with identical voltage levels. The proposed converter contains a reduced number of components compared to the neutral point clamped (NPC) or active-NPC topologies (ANPC) for the same number of output voltage levels, since it does not require diode or active switch clamping to a neutral point. Moreover, no floating capacitors with asymmetric voltage levels are employed, thereby simplifying the capacitor voltage balancing. The switching operation principles, modulation technique and control scheme for supplying a single-phase resistive-inductive load are addressed in detail. The proposed four-level inverter allows generating an additional output voltage level with the same semiconductor count as conventional three-level inverters such as NPC and ANPC which allows a superior waveform quality, with a THDv reduction of 32.69% in comparison the clamped inverters. Experimental tests carried out in a laboratory-scale setup verify the feasibility of the proposed topology.
AB - In this paper, a novel four-level single-phase multilevel converter is introduced, consisting of six active switches arranged in a quasi-nested configuration. The proposed topology synthesizes its output voltage levels with respect to a floating neutral point, using four cascaded capacitors with identical voltage levels. The proposed converter contains a reduced number of components compared to the neutral point clamped (NPC) or active-NPC topologies (ANPC) for the same number of output voltage levels, since it does not require diode or active switch clamping to a neutral point. Moreover, no floating capacitors with asymmetric voltage levels are employed, thereby simplifying the capacitor voltage balancing. The switching operation principles, modulation technique and control scheme for supplying a single-phase resistive-inductive load are addressed in detail. The proposed four-level inverter allows generating an additional output voltage level with the same semiconductor count as conventional three-level inverters such as NPC and ANPC which allows a superior waveform quality, with a THDv reduction of 32.69% in comparison the clamped inverters. Experimental tests carried out in a laboratory-scale setup verify the feasibility of the proposed topology.
KW - DC-link voltage self-balancing
KW - Levelshifted PWM
KW - Multilevel inverter
KW - Proportional multi resonant controller
KW - Quasi-Nested topology
KW - Reduced active switches topology
KW - Single-phase applications
UR - http://www.scopus.com/inward/record.url?scp=85099540098&partnerID=8YFLogxK
U2 - 10.3390/electronics10030233
DO - 10.3390/electronics10030233
M3 - Article
AN - SCOPUS:85099540098
VL - 10
SP - 1
EP - 19
JO - Electronics (Switzerland)
JF - Electronics (Switzerland)
SN - 2079-9292
IS - 3
M1 - 233
ER -